1. Field of Invention
This invention relates generally to semiconductor memories and specifically to a nonvolatile Flash memory cell and an associated array architecture.
2. Description of Related Art
Recent advances in the semiconductor industry have led to the development of a PMOS floating gate (FG) memory cell, such as that disclosed by T. Ohnakado et al in an article entitled "Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a P-channel Cell," IEEE International Electron Devices Meeting Technical Digest, 1995, pp.279-282, incorporated herein by reference. A PMOS FG cell 10 of the type disclosed in the above-referenced article is shown in FIG. 1. The cell 10 is formed in an n- well region 12 of a p-substrate 14. A p+ source 16 and a p+ drain 18 are formed in the n- well region 12. Dopants of the n conductivity type such as, for instance, Phosphorus ions, are implanted into a channel region 20 to realize an enhancement mode device. An n conductivity type polysilicon floating gate 22 is insulated from the n- well region 12 by a tunnel oxide layer 24. Preferably, the tunnel oxide layer 24 is approximately 110 .ANG. thick. A control gate 26 is insulated from the floating gate 22 by an insulating layer 28.
The cell 10 is programmed by applying approximately 10 volts to the control gate 26, approximately -6 volts to the p+ drain 18, floating the p+ source 16, and grounding the n- well region 12. Under these bias conditions, hot electrons induced by band-to-band tunneling (BTBT) are injected into the floating gate 22. The resultant accumulation of charge on the floating gate 22 increases the threshold voltage V.sub.T of the cell 10 to approximately -2.5 volts. Thus, when programmed, the cell 10 operates as an enhancement mode device.
The cell 10 is erased by applying approximately -10 volts to the control gate 26, floating the p+ drain 18, and applying approximately 10 volts to the p+ source 16 and to the n- well region 12. Under these bias conditions, electrons are ejected from the floating gate 22 by Fowler Norheim (FN) tunneling, thereby returning the threshold voltage V.sub.T of the cell 10 to approximately -4.2 volts.
The cell 10 is read by applying approximately -3.3 volts and approximately -1 volt to the control gate 26 and to the p+ drain 18, respectively, while grounding the p+ source 16 and the n- well region 12. Under these bias conditions, the cell 10 conducts a channel current if in a programmed state.
The operation of the cell 10, both in isolation and part of an array architecture, is the subject of Japanese Laid-Open Publication No. 9-8153 entitled "Nonvolatile Semiconductor Memory Device," published Jan. 10, 1997 and assigned to Mitsubishi Electric Corporation (Mitsubishi). Accordingly, the cell 10 is hereinafter referred to as the Mitsubishi cell 10.
In the above-referenced article, the authors teach that one of the primary advantages realized by the cell 10 is its high scalability which, the authors state, is about the same for a conventional PMOS transistor. Further, the authors teach that BTBT induced hot electron injection programming allows for superior programming speeds, as compared to that of FN tunneling. The article provides that the maximum programming efficiency of BTBT induced hot electron injection, measured as the ratio of gate current to drain current (I.sub.G /I.sub.D), is between one and two orders of magnitude greater than the maximum programming efficiency realized by FN tunneling. The cell 10 has a maximum programmed speed of about 50 .mu.s.
The Japanese Laid Open Publication No. 9-8153 discloses a NOR array architecture having a plurality of memory cells of the type disclosed in the above-referenced article, i.e., the Mitsubishi cell 10 (FIG. 1). A NOR array 30 of the type disclosed in the Japanese Laid Open Publication No. 9-8153 is shown in FIG. 2 to include sixteen of the Mitsubishi cells 10. The control gates 26 of the cells 10 in a common row of the array 30 are connected to a word line WL. The p+ drains 18 of the cells 10 in a common column are connected to a bit line BL. The p+ sources 16 of the cells 10 in a common row are connected to a common source line CS.
Note that the memory cells in the NOR array 30 consist only of the Mitsubishi FG cell 10. Arrays of this type are commonly known as a 1T cell array, where a 1T cell is defined as a memory cell that includes only one transistor. Since a 1T cell such as, for instance, the cell 10 of the NOR array 30, does not include select transistors, its cell area is minimized. Thus, when used as a 1T memory cell, as in the array 30, the highly scalable Mitsubishi cell 10 allows for maximum cell density.
In other embodiments of the Japanese Laid Open Publication No. 9-8153, each bit line BL of the array 30 is divided along page boundaries, where each bit line segment is connected to a global bit line via a select transistor. The resulting array architecture, thus having segmented, or divided, bit lines, is commonly known as a DINOR (DIvided bit line NOR) cell array, and is the subject of U.S. Pat. No. 5,554,867, issued to Ajika et al on Sep. 10, 1996, and assigned to Mitsubishi. In that patent, Ajika et al teach that a primary advantage of the DINOR array architecture is a further reduction in cell area. Accordingly, using the FG transistor 10 as a 1T memory cell in a DINOR cell architecture allows for even greater cell density.
Although advantageous in many respects over other memory cells, the Mitsubishi cell 10 is susceptible to BTBT disturb during programming and reading. For instance, when programming the cell 10(0,0) of the array 30, the selected bit line BL0 is held at approximately -6 volts, the selected word line WL0 is pulsed to approximately 8 volts, and the unselected word lines WL1-WL3 are grounded. The common source lines CS are floating. As described above, these bias conditions facilitate programming of the selected cell 10(0,0) via BTBT induced hot electron injection. However, during programming of the selected cell 10(0,0), the respective drains 18 of the unselected cells 10 in the same column as the selected cell, i.e., the cells 10(1,0), 10(2,0), and 10(3,0), are directly coupled to the selected bit line BL0 and, thus, are at approximately -6 volts.
Thus, within each of these unselected cells 10, the resulting voltage differential between the p+ drain 18 and the n- well region 12, which is approximately -6 volts, is sufficient to cause electrons to accelerate from the p+ drain 18 to the n- well region 12 via BTBT. Since the respective control gates 26 of the unselected cells 10(1,0), 10(2,0), and 10(3,0) are grounded, within each of these unselected cells 10 approximately -1 volt is coupled from the p+ drain 18 to the floating gate 22 (assuming a typical drain to floating gate coupling of 15-20%). This voltage difference between the respective p+ drains 18 and floating gates 22 of these unselected cells 10 is sufficient to inject the hot electrons generated via BTBT into the respective floating gates 22 thereof. Accordingly, when programming the selected cell 10(0,0), these two aforementioned fields created within the unselected cells 10(1,0), 10(2,0), and 10(3,0) result in an unintended programming of these unselected cells 10 via BTBT induced hot electron injection. As a result of this BTBT disturb, data integrity is compromised.